Today we are in the age of Digital Convergence seeing a major change in the way digital electronics systems are designed. Examples of such convergence can be seen in Microsoft's Xbox (From IT to Entertainment), Apple's iPhone (From IT to Telecommunication), and Sony's Vaio (From Consumer Electronics to IT). This innovative look at technology has redefined road maps and business objectives of major corporations.
In the past, many digital designers successfully ignored issues related to verification, designing their systems and checking the functionality using basic test benches and simulation environments. Only the designers of supercomputers and high-speed communication systems looked beyond the digital abstraction. This is no longer the case. As technology has advanced, the systems-level engineering problems of digital systems have become critical to the success of all digital systems. As technology continues to advance, issues of Complex SoC integration, Verification at various phases of chip development, Timing closure, Power Management & Energy efficiency, and Silicon Testing have become critically important. As designs become highly complex and dense the importance and challenges in verification grows grows exponentially. The number and speed of gates on a chip have increased faster than the number and speed of pins, making inter-chip communication a system bottleneck and placing a premium on timing conventions. With reduced supply voltages and higher currents, power distribution becomes a more challenging engineering problem. At high frequencies timing conventions must be carefully designed to prevent skew and jitter of clock signals from degrading system performance. Because of these trends, we have found motivation to address the basics in Verification, Timing, Power, and Testing to help solve higher problems in designing complex systems.
First, the success and acceptance of The Digital Electronics Blog in the ASIC-SoC(VLSI ) & EDA community.
Second, in our research building high-speed digital systems (Wireless, Wireline, Security and other complex systems) we came across a number of techniques that overcame the limitations of conventional methods. We are eager to share these methods and the engineering science behind them.
Our third motivation was to avoid repetitions of many disasters we encountered in our interactions with industry. Over a year was spent at one company chasing bugs before that system would operate reliably. Another system went through several iterations of ASICs due to timing problems. A third system failed periodically due to on-chip power supply fluctuations. A fourth system product was delayed by six months because of a subtle failure in the flip-flops used throughout a custom chip design. These problems delayed system delivery by months to years and in some cases directly contributed to the failure of companies. Quick and lasting fixes rarely exist for these types of problems; however, they could have been easily avoided by proper design if the
engineers involved had been knowledgeable in basics. By developing this website we hope to help eradicate the
widespread ignorance, and often misinformation, in these areas, and in doing so, help avoid disasters of this kind in the future.
We hope this site will be useful to build your career as an engineer who builds defect free products.
Please check out the individual chapters lined below for your convenience and we are eagerly looking forward to your continued support and criticisms.
Good Luck and Best Wishes!
Convergence image courtesy: http://www.adkorea.com/
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